ST STM32G473 - Figure 279. Counter Timing Diagram, Internal Clock Divided by 2; Figure 280. Counter Timing Diagram, Internal Clock Divided by 4

RM0440 Rev 4 1099/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
1226
Figure 279. Counter timing diagram, internal clock divided by 2
Figure 280. Counter timing diagram, internal clock divided by 4
MSv62306V1
tim_psc_ck
CEN
tim_cnt_ck
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0002
0001
0000
0036
0035
0034
0033
MSv62307V1
0000 0001
0001
0000
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
CEN