RM0440 Rev 4 777/2126
RM0440 Voltage reference buffer (VREFBUF)
777
23.4.2 VREFBUF calibration control register (VREFBUF_CCR)
Address offset: 0x04
Reset value: 0x0000 00XX
23.4.3 VREFBUF register map
The following table gives the VREFBUF register map and the reset values.
Refer to Section 2.2 on page 80 for the register boundary addresses.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIM[5:0]
rw rw rw rw rw rw
Bits 31:6 Reserved, must be kept at reset value.
Bits 5:0 TRIM[5:0]: Trimming code
The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and
updated according the mechanism described below.
Reset:
TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash
memory during the production test.
VRS change:
TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting)
stored in the Flash memory during the production test.
Write in TRIM[5:0]:
User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the
control of the trimming value with VRS (until the device is reset).
Table 194. VREFBUF register map and reset values
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
VREFBUF_CSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VRR
VRS[1:0]
HIZ
ENVR
Reset value 00010
0x04
VREFBUF_CCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TRIM[5:0]
Reset value xxxxxx
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