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Voltage reference buffer (VREFBUF) RM0440

776/2126 RM0440 Rev 4

23.4 VREFBUF registers

23.4.1 VREFBUF control and status register (VREFBUF_CSR)

Address offset: 0x00

Reset value: 0x0000 0002

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VRS[1:0] VRR Res. HIZ ENVR

rw rw r rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:4 VRS[1:0]: Voltage reference scale

These bits select the value generated by the voltage reference buffer.

00: Voltage reference set to 2.048 V

01: Voltage reference set to 2.5 V

10: Voltage reference set to 2.90 V

11: Reserved

Bit 3 VRR: Voltage reference buffer ready

0: the voltage reference buffer output is not ready.

1: the voltage reference buffer output reached the requested level.

Bit 2 Reserved, must be kept at reset value.

Bit 1 HIZ: High impedance mode

This bit controls the analog switch to connect or not the V

REF+

pin.

0: V

REF+

pin is internally connected to the voltage reference buffer output.

1: V

REF+

pin is high impedance.

Refer to Table 193: VREF buffer modes for the mode descriptions depending on ENVR bit

configuration.

Bit 0 ENVR: Voltage reference buffer mode enable

This bit is used to enable the voltage reference buffer mode.

0: Internal voltage reference mode disable (external voltage reference mode).

1: Internal voltage reference mode (reference buffer enable or hold mode) enable.

ST STM32G473 User Manual

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