RM0440 Rev 4 447/2126
RM0440 Extended interrupts and events controller (EXTI)
460
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
For the configurable lines, an interrupt/event request can also be generated by software by
writing a ‘1’ in the software interrupt/event register.
Note: The interrupts or events associated to the direct lines are triggered only when the system is
in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI.
15.3.1 EXTI block diagram
The extended interrupt/event block diagram is shown on Figure 35.
Figure 35. Configurable interrupt/event block diagram
15.3.2 Wakeup event management
The STM32G4 Series is able to handle external or internal events in order to wake up the
core (WFE). The wakeup event can be generated either by:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex
TM
-M4 System Control register. When the MCU
resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared
• or by configuring an EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel
pending bit as the pending bit corresponding to the event line is not set.
Peripheral interface
Edge detect
circuit
APB bus
PCLK
Interrupts
Software
interrupt
event
register
Rising
trigger
selection
register
Pending
request
register
MS33393V1
Interrupt
mask
register
Falling
trigger
selection
register
Event
mask
register
Rising
edge
detect
Stop mode
Direct events
Configurable
events
Events
Wakeup
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