RM0440 Rev 4 1803/2126
RM0440 Serial audio interface (SAI)
1858
Generation of the bit clock (SCK_x)
The clock generator provides the bit clock (SCK_x) when the audio block is defined as
Master. The frame synchronization (FS_x) is also derived from the signals provided by the
clock generator.
In Slave mode, the value of NODIV and OSR fields are ignored, and the SCK_x clock is not
generated.
The bit clock strobing edge of SCK_x can be configured through the CKSTR fields, which is
functional both in master and slave mode.
Figure 614 illustrates the architecture of the audio block clock generator.
Figure 614. Audio block clock generator overview
The NODIV bit must be used to force the ratio between the master clock (MCLK_x) and the
frame synchronization (FS_x) frequency to 256 or 512.
• If NODIV is set to 0, the frequency ratio between the frame synchronization and the
master clock is fixed to 512 or 256, according to OSR value, but the frame length must
be a power of 2. More details are given hereafter.
• If NODIV is set to 1, the application can adjust the frequency of the bit clock (SCK_x)
via MCKDIV. In addition there is no restriction on the frame length value as long as the
frame length is bigger or equal to 8 (i.e. FRL[7:0] > 6). The frame synchronization
frequency depends on MCKDIV and frame length (FRL[7:0]). In that case, the
frequency of the MCLK_x is equal to the SCK_x.
The NODIV, MCKEN, SAIEN, OVR, CKSTR and MCKDIV[5:0] bits belong to the SAI_xCR1
register, while FRL[7:0] belongs to SAI_xFRCR.
MSv43706V3
Clock divider
sai_x_ker_
ck
MCLK_x
MCKDIV[5:0]
SCK_x
NODIV
0
1
FS_x
FRL[7:0]
SAI clock generator x
OSR
÷2
0
1
÷
÷ (FRL+1)
FRL[7:0]
[0]
[0]: FRL+1 must be a power of 2 when NOMCK = 0
256
FRL+1
Audio Block x
NODIV
MCKEN
SAIEN for block x
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