Serial audio interface (SAI) RM0440
1804/2126 RM0440 Rev 4
Clock generator programming when NODIV = 0
In that case, MCLK_x frequency will be:
• F
MCLK_x
= 256 x F
FS_x
if OSR = 0
• F
MCLK_x
= 512 x F
FS_x
if OSR = 1
When MCKDIV is different from 0, MCLK_x frequency is given by the formula below:
The frame synchronization frequency is given by:
The bit clock frequency (SCK_x) is given by the following formula:
Note: When NODIV is equal to 0, (FRL+1) must be a power of two. In addition (FRL+1) must
range between 8 and 256. (FRL +1) represents the number of bit clock in the audio frame.
When MCKDIV division ratio is odd, the MCLK duty cycle will not be 50%. The bit clock
signal (SCK_x) can also have a duty cycle different from 50% if MCKDIV is odd, if OSR is
equal to 0, and if (FRL+1) = 2
8
.
It is recommended, to program MCKDIV to an even value or to big values (higher than 10).
Note that MCKDIV = 0 gives the same result as MCKDIV = 1.
Clock generator programming when NODIV = 1
When MCKDIV is different from 0, the frequency of the bit clock (SCK_x) is given in the
formula below:
The frequency of the frame synchronization (FS_x) in given by the following formula:
Note: When NODIV is set to 1, (FRL+1) can take any values from 8 to 256.
Note that MCKDIV = 0 gives the same result as MCKDIV = 1.
F
MCLK_x
F
sai_x_ker_ck
MCKDIV
-----------------------------------
=
F
FS_x
F
sai_x_ker_ck
MCKDIV OSR 1+()256××
----------------------------------------------------------------------------
=
F
SCK_x
F
sai_x_ker_ck
FRL 1+()×
MCKDIV OSR 1+()× 256×
----------------------------------------------------------------------------
=
F
SCK_x
F
MCLK_x
F
sai_x_ker_ck
MCKDIV
-----------------------------------
==
F
FS_x
F
sai_x_ker_ck
FRL 1+()MCKDIV×
----------------------------------------------------------
=
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