RM0440 Rev 4 191/2126
RM0440 Embedded Flash memory (FLASH) for category 2 devices
228
Increasing the CPU frequency:
1. Program the new number of wait states to the LATENCY bits in the Flash access
control register (FLASH_ACR).
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register.
3. Analyze the change of CPU frequency change caused either by:
– changing clock source defined by SW bits in RCC_CFGR register
– or by CPU clock prescaller defined by HPRE bits in RCC_CFGR
If some of above two steps decreases the CPU frequency, firstly perform this step and then
the rest. Otherwise modify The CPU clock source by writing the SW bits in the RCC_CFGR
register and then (if needed) modify the CPU clock prescaler by writing the HPRE bits in
RCC_CFGR.
4. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Decreasing the CPU frequency:
1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
3. Analyze the change of CPU frequency change caused either by:
– changing clock source defined by SW bits in RCC_CFGR register
– or by CPU clock prescaller defined by HPRE bits in RCC_CFGR
If some of above two steps increases the CPU frequency, firstly perform another step and
then this step. Otherwise modify The CPU clock source by writing the SW bits in the
RCC_CFGR register and then (if needed) modify the CPU clock prescaler by writing the
HPRE bits in RCC_CFGR.
4. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
5. Program the new number of wait states to the LATENCY bits in Flash access control
register (FLASH_ACR).
6. Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register.
5.3.4 Adaptive real-time memory accelerator (ART Accelerator)
The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm
®
Cortex
®
-M4 with FPU processors. It balances the inherent
performance advantage of the Arm
®
Cortex
®
-M4 with FPU over Flash memory
technologies, which normally requires the processor to wait for the Flash memory at higher
operating frequencies.
To release the processor full performance, the accelerator implements an instruction
prefetch queue and branch cache which increases program execution speed from the 64-
bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the
ART accelerator is equivalent to 0 wait state program execution from Flash memory at a
CPU frequency up to 170 MHz.
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