ST STM32G473 User Manual

RM0440 Rev 4 557/2126
RM0440 Flexible static memory controller (FSMC)
571
19.7 NAND Flash controller
The FMC generates the appropriate signal timings to drive the following types of device:
• 8- and 16-bit NAND Flash memories
The NAND bank is configured through dedicated registers (Section 19.7.7). The
programmable memory parameters include access timings (shown in Table 149) and ECC
configuration.
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 CNTB4EN: Counter Bank 4 enable
This bit enables the chip select counter for PSRAM/NOR Bank 4.
0: Counter disabled for Bank 4
1: Counter enabled for Bank 4
Bit 18 CNTB3EN: Counter Bank 3 enable
This bit enables the chip select counter for PSRAM/NOR Bank 3.
0: Counter disabled for Bank 3.
1: Counter enabled for Bank 3
Bit 17 CNTB2EN: Counter Bank 2 enable
This bit enables the chip select counter for PSRAM/NOR Bank 2.
0: Counter disabled for Bank 2
1: Counter enabled for Bank 2
Bit 16 CNTB1EN: Counter Bank 1 enable
This bit enables the chip select counter for PSRAM/NOR Bank 1.
0: Counter disabled for Bank 1
1: Counter enabled for Bank 1
Bits 15:0 CSCOUNT[15:0]: Chip select counter.
These bits are written by software to define the maximum chip select low pulse duration. It is
expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous
accesses.
The counter is disabled if the programmed value is 0.
Table 149. Programmable NAND Flash access parameters
Parameter Function Access mode Unit Min. Max.
Memory setup
time
Number of clock cycles (HCLK)
required to set up the address
before the command assertion
Read/Write
AHB clock cycle
(HCLK)
1 255
Memory wait
Minimum duration (in HCLK clock
cycles) of the command assertion
Read/Write
AHB clock cycle
(HCLK)
2 255

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English