RM0440 Rev 4 209/2126
RM0440 Embedded Flash memory (FLASH) for category 2 devices
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5.5.2 Proprietary code readout protection (PCROP)
Apart of the flash memory can be protected against read and write from third parties. The
protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction
code, while all other accesses (DMA, debug and CPU data read, write and erase) are
strictly prohibited. The PCROP area has a double word (64-bit) granularity. An additional
option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP
protection is changed from Level 1 to Level 0 (refer to Changing the Read protection level).
Each PCROP area is defined by a start page offset and an end page offset related to the
physical Flash address. These offsets are defined in the PCROP address registers Flash
PCROP1 Start address register (FLASH_PCROP1SR), Flash PCROP1 End address
register (FLASH_PCROP1ER).
• The PCROPx (x = 1) area is defined from the address: Flash memory base address +
[PCROPx_STRT x 0x8] (included) to the address: Flash memory base address +
[(PCROPx_END+1) x 0x8] (excluded). The minimum PCROP area size is two double-
words (128 bits).
For example, to protect by PCROP from the address 0x0806 2F80 (included) to the address
0x0807 0004 (included):
• if boot in flash is selected, FLASH_PCROP1SR and FLASH_PCROP1ER registers
must be programmed with:
– PCROP1_STRT = 0xC5F0.
– PCROP1_END = 0xE000.
Option bytes
1 Yes Yes
(3)
Yes Yes Yes
(3)
Yes
2 Yes No No N/A N/A N/A
OTP
1 Yes Yes
(4)
N/A No No N/A
2 Yes Yes
(4)
N/A N/A N/A N/A
Backup
registers
1 Yes Yes N/A No No No
(5)
2 Yes Yes N/A N/A N/A N/A
CCM SRAM
1 Yes Yes N/A No No No
(6)
2 Yes Yes N/A N/A N/A N/A
1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. The Flash main memory is erased when the RDP option byte is programmed with all level protections disabled (0xAA).
4. OTP can only be written once.
5. The backup registers are erased when RDP changes from level 1 to level 0.
6. The CCM SRAM is erased when RDP changes from level 1 to level 0.
Table 33. Access status versus protection level and execution modes (continued)
Area
Protection
level
User execution (BootFromFlash)
Debug/ BootFromRam/
BootFromLoader
(1)
Read Write Erase Read Write Erase
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