ST STM32G473 User Manual

RM0440 Rev 4 275/2126
RM0440 Reset and clock control (RCC)
338
All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except:
• The 48 MHz clock, used for USB device FS, and RNG. This clock is derived (selected
by software) from one of the four following sources:
– PLL “Q” Clock
– HSI48 internal oscillator
When available, the HSI48 48 MHz clock can be coupled to the clock recovery system
allowing adequate clock connection for the USB OTG FS (Crystal less solution).
• The ADCs clock which is derived (selected by software) from one of the following
sources:
– System clock (SYSCLK)
– PLL “P” clock
• The U(S)ARTs clocks which are derived (selected by software) from one of the four
following sources:
– System clock (SYSCLK)
–HSI16 clock
– LSE clock
– APB1 or APB2 clock (PCLK1 or PCLK2 depending on which APB is mapped the
U(S)ART)
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
• The I
2
Cs clocks which are derived (selected by software) from one of the three
following sources:
– System clock (SYSCLK)
–HSI16 clock
– APB1 clock (PCLK1)
The wakeup from Stop mode is supported only when the clock is HSI16.
• The SAI1 clock which is derived (selected by software) from one of the following
sources:
– an external clock mapped on I2S_CKIN
– System clock
– PLL “Q” clock
–HSI16 clock
• The QUADSPI kernel clock which is derived (selected by software) from one of the
following sources:
– System clock,
– PLL “Q” clock
– HSI16 clock
• The low-power timer (LPTIM1) clock which is derived (selected by software) from one
of the five following sources:
–LSI clock
– LSE clock
–HSI16 clock
– APB1 clock (PCLK1)
– External clock mapped on LPTIMx_IN1
The functionality in Stop mode (including wakeup) is supported only when the clock is

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English