ST STM32G473

RM0440 Rev 4 1311/2126
RM0440 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
1343
Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection (see bits 21:20 for TS[4:3])
This bit-field selects the trigger input to be used to synchronize the counter.
00000: Internal trigger 0 (tim_itr0)
00001: Internal trigger 1 (tim_itr1)
00010: Internal trigger 2 (tim_itr2)
00011: Internal trigger 3 (tim_itr3)
00100: tim_ti1 edge detector (tim_ti1f_ed)
00101: Filtered timer input 1 (tim_ti1fp1)
00110: Filtered timer input 2 (tim_ti2fp2)
00111: External trigger input (tim_etrf)
01000: Internal trigger 4 (tim_itr4)
01001: Internal trigger 5 (tim_itr5)
01010: Internal trigger 6 (tim_itr6)
01011: Internal trigger 7 (tim_itr7)
01100: Internal trigger 8 (tim_itr8)
01101: Internal trigger 9 (tim_itr9)
01110: Internal trigger 10 (tim_itr10)
01111: Internal trigger 11 (tim_itr11)
Others: Reserved
See Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific
implementation details.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 OCCS: OCREF clear selection
This bit is used to select the OCREF clear source
0: tim_ocref_clr_int is connected to the tim_ocref_clr input
1: tim_ocref_clr_int is connected to tim_etrf
Note: If the OCREF clear selection feature is not supported, this bit is reserved and forced by
hardware to ‘0’. Section 29.3: TIM2/TIM3/TIM4/TIM5 implementation.