ST STM32G473 User Manual

General-purpose timers (TIM15/TIM16/TIM17) RM0440
1402/2126 RM0440 Rev 4
Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode
These bits define the behavior of the output reference signal tim_oc1ref from which tim_oc1
and tim_oc1n are derived. tim_oc1ref is active high whereas tim_oc1 and tim_oc1n active
level depends on CC1P and CC1NP bits.
0000: Frozen - The comparison between the output compare register TIM15_CCR1 and the
counter TIM15_CNT has no effect on the outputs.
0001: Set channel 1 to active level on match. tim_oc1ref signal is forced high when the
counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1).
0010: Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the
counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1).
0011: Toggle - tim_oc1ref toggles when TIM15_CNT=TIM15_CCR1.
0100: Force inactive level - tim_oc1ref is forced low.
0101: Force active level - tim_oc1ref is forced high.
0110: PWM mode 1 - Channel 1 is active as long as TIM15_CNT<TIM15_CCR1 else
inactive.
0111: PWM mode 2 - Channel 1 is inactive as long as TIM15_CNT<TIM15_CCR1 else
active.
1000: Retrigerrable
OPM mode 1 - In up-counting mode, the channel is active until a trigger
event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
mode 1 and the channels becomes active again at the next update. In down-counting
mode, the channel is inactive until a trigger event is detected (on tim_trgi signal).
Then, a comparison is performed as in PWM mode 1 and the channels becomes
inactive again at the next update.
1001: Retrigerrable
OPM mode 2 - In up-counting mode, the channel is inactive until a
trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
PWM mode 2 and the channels becomes inactive again at the next update. In down-
counting mode, the channel is active until a trigger event is detected (on tim_trgi
signal). Then, a comparison is performed as in PWM mode 1 and the channels
becomes active again at the next update.
1010: Reserved
1011: Reserved
1100: Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1.
tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
1101: Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2.
tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
1110: Reserved,
1111: Reserved,
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIM15_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: In PWM mode, the tim_ocxref level changes only when the result of the comparison
changes or when the output compare mode switches from “frozen” mode to “PWM”
mode.
3: On channels that have a complementary output, this bit field is preloaded. If
the CCPC bit is set in the TIM15_CR2 register then the OC1M active bits take
the new value from the preloaded bits only when a COM event is generated.

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English