General-purpose timers (TIM15/TIM16/TIM17) RM0440
1404/2126 RM0440 Rev 4
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
CC1 channel configured as output:
0: tim_oc1n active high
1: tim_oc1n active low
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define the polarity of tim_ti1fp1 and tim_ti2fp1.
Refer to CC1P description.
Note: 1.This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK
bits in TIM15_BDTR register) and CC1S=”00” (the channel is configured in output).
2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit
is set in the TIM15_CR2 register then the CC1NP active bit takes the new value from
the preloaded bit only when a Commutation event is generated.
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0:Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1,
OIS1N and CC1E bits.
1:On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: tim_oc1 active high
1: tim_oc1 active low
CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of tim_ti1fp1
and tim_ti2fp1 for trigger or capture operations.
00: non-inverted/rising edge. The circuit is sensitive to tim_tixfp1 rising edge (capture or
trigger operations in reset, external clock or trigger mode), tim_tixfp1 is not inverted
(trigger operation in gated mode).
01: inverted/falling edge. The circuit is sensitive to tim_tixfp1 falling edge (capture or trigger
operations in reset, external clock or trigger mode), tim_tixfp1 is inverted (trigger
operation in gated mode).
10: Reserved
11: non-inverted/both edges. The circuit is sensitive to both tim_tixfp1 rising and falling
edges (capture or trigger operations in reset, external clock or trigger mode), tim_tixfp1
is not inverted (trigger operation in gated mode).
Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK
bits in TIM15_BDTR register).
2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit
is set in the TIM15_CR2 register then the CC1P active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
Bit 0 CC1E: Capture/Compare 1 output enable
CC1 channel configured as output:
0:Off - tim_oc1 is not active. tim_oc1 level is then function of MOE, OSSI, OSSR, OIS1,
OIS1N and CC1NE bits.
1:On - tim_oc1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input: This bit determines if a capture of the counter value can
actually be done into the input capture/compare register 1 (TIM15_CCR1) or not.
0: Capture disabled
1: Capture enabled
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