Real-time clock (RTC) RM0440
1570/2126 RM0440 Rev 4
35.6.15 RTC alarm A sub second register (RTC_ALRMASSR)
This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1547.
Address offset: 0x44
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MASKSS[3:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw
1514131211109876543210
Res. SS[14:0]
rw rw rw rw rw rw rw rw rw rw rw rw w rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0:No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1:SS[14:1] are don’t care in alarm A comparison. Only SS[0] is compared.
2:SS[14:2] are don’t care in alarm A comparison. Only SS[1:0] are compared.
3:SS[14:3] are don’t care in alarm A comparison. Only SS[2:0] are compared.
...
12:SS[14:12] are don’t care in alarm A comparison. SS[11:0] are compared.
13:SS[14:13] are don’t care in alarm A comparison. SS[12:0] are compared.
14:SS[14] is don’t care in alarm A comparison. SS[13:0] are compared.
15:All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can
be different from 0 only after a shift operation.
Bits 23:15 Reserved, must be kept at reset value.
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine
if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
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