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Independent watchdog (IWDG) RM0440

1934/2126 RM0440 Rev 4

42.4.3 IWDG reload register (IWDG_RLR)

Address offset: 0x08

Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. RL[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 RL[11:0]: Watchdog counter reload value

These bits are write access protected see Register access protection. They are written by

software to define the value to be loaded in the watchdog counter each time the value 0xAAAA

is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this

value. The timeout period is a function of this value and the clock prescaler. Refer to the

datasheet for the timeout information.

The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the

reload value.

Note: Reading this register returns the reload value from the V

voltage domain. This value

may not be up to date/valid if a write operation to this register is ongoing on it. For this

reason the value read from this register is valid only when the RVU bit in the IWDG

status register (IWDG_SR) is reset.

ST STM32G473 User Manual

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