Reset and clock control (RCC) RM0440
288/2126 RM0440 Rev 4
during sleep mode. The AHB to APB bridge clocks are disabled by hardware during
Sleep mode when all the clocks of the peripherals connected to them are disabled.
• Stop modes (Stop 0 and Stop 1) stops all the clocks in the V
CORE
domain and disables
the PLL, the HSI16, and the HSE oscillators.
All U(S)ARTs, LPUARTs and I
2
Cs have the capability to enable the HSI16 oscillator
even when the MCU is in Stop mode (if HSI16 is selected as the clock source for that
peripheral).
All U(S)ARTs and LPUARTs can also be driven by the LSE oscillator when the system
is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE
oscillator is enabled (LSEON). In that case the LSE remains always ON in Stop mode
(they do not have the capability to turn on the LSE oscillator).
• Standby and Shutdown modes stops all the clocks in the V
CORE
domain and disables
the PLL, the HSI16, and the HSE oscillators.
The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When leaving the Stop modes (Stop 0, Stop 1 or standby), the system clock is HSI16.
If a Flash memory programming operation is on going, Stop, Standby and Shutdown modes
entry is delayed until the Flash memory interface access is finished. If an access to the APB
domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB
access is finished.
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