To Next Page

To Previous Page

RM0440 Rev 4 311/2126

RM0440 Reset and clock control (RCC)

338

7.4.16 AHB3 peripheral clock enable register(RCC_AHB3ENR)

Address offset: 0x50

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not

supported.

Bit 2 GPIOCEN: IO port C clock enable

Set and cleared by software.

0: IO port C clock disabled

1: IO port C clock enabled

Bit 1 GPIOBEN: IO port B clock enable

Set and cleared by software.

0: IO port B clock disabled

1: IO port B clock enabled

Bit 0 GPIOAEN: IO port A clock enable

Set and cleared by software.

0: IO port A clock disabled

1: IO port A clock enabled

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. QSPIEN Res. Res. Res. Res. Res. Res. Res.

FMC

rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 QSPIEN: QUADSPI memory interface clock enable

Set and cleared by software.

0: QUADSPI clock disable

1: QUADSPI clock enable

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 FMCEN: Flexible static memory controller clock enable

Set and cleared by software.

0: FSMC clock disable

1: FSMC clock enable

ST STM32G473 User Manual

Questions and Answers: