ST STM32G473 User Manual

RM0440 Rev 4 319/2126
RM0440 Reset and clock control (RCC)
338
7.4.21 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
Address offset: 0x6C
Reset value: 0x050F 667F
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
RNG
EN
Res.
AESM
EN
Res. Res. Res. Res.
DAC4
SMEN
DAC3
SMEN
DAC2
SMEN
DAC1
SMEN
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
ADC345
SMEN
ADC12
SMEN
Res. Res.
SRAM2
SMEN
CCMSRAM
SMEN
Res. Res.
GPIOG
SMEN
GPIOF
SMEN
GPIOE
SMEN
GPIOD
SMEN
GPIOC
SMEN
GPIOB
SMEN
GPIOA
SMEN
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 RNGEN: RNG enable
Set and cleared by software.
0: RNG disabled
1: RNG enabled
Bit 25 Reserved, must be kept at reset value.
Bit 24 AESMEN: AESM clocks enable
Set and cleared by software.
0: AESM clocks disabled
1: AESM clocks enabled
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 DAC4SMEN: DAC4 clock enable
Set and cleared by software.
0: DAC4 clock disabled
1: DAC4 clock enabled during sleep and stop modes
Bit 18 DAC3SMEN: DAC3 clock enable
Set and cleared by software.
0: DAC3 clock disabled
1: DAC3 clock enabled during sleep and stop modes
Bit 17 DAC2SMEN: DAC2 clock enable
Set and cleared by software.
0: DAC2 clock disabled
1: DAC2 clock enabled during sleep and stop modes
Bit 16 DAC1SMEN: DAC1 clock enable
Set and cleared by software.
0: DAC1 clock disabled
1: DAC1 clock enabled during sleep and stop modes
Bit 15 Reserved, must be kept at reset value.

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English