STC micro STC8A8K64D4 Series - Page 234

STC8A8K64D4 Series Manual
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Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_M2M_CFG
FA00H
M2MIE
-
TXACO
RXACO
M2MIP[1:0]
M2MPTY[1:0]
DMA_ADC_CFG
FA10H
ADCIE
-
-
-
ADCMIP[1:0]
ADCPTY[1:0]
DMA_SPI_CFG
FA20H
SPIIE
ACT_TX
ACT_RX
-
SPIIP[1:0]
SPIPTY[1:0]
DMA_UR1T_CFG
FA30H
UR1TIE
-
-
-
UR1TIP[1:0]
UR1TPTY[1:0]
DMA_UR1R_CFG
FA38H
UR1RIE
-
-
-
UR1RIP[1:0]
UR1RPTY[1:0]
DMA_UR2T_CFG
FA40H
UR2TIE
-
-
-
UR2TIP[1:0]
UR2TPTY[1:0]
DMA_UR2R_CFG
FA48H
UR2RIE
-
-
-
UR2RIP[1:0]
UR2RPTY[1:0]
DMA_UR3T_CFG
FA50H
UR3TIE
-
-
-
UR3TIP[1:0]
UR3TPTY[1:0]
DMA_UR3R_CFG
FA58H
UR3RIE
-
-
-
UR3RIP[1:0]
UR3RPTY[1:0]
DMA_UR3R_CFG
FA60H
UR4TIE
-
-
-
UR4TIP[1:0]
UR4TPTY[1:0]
DMA_UR4R_CFG
FA68H
UR4RIE
-
-
-
UR4RIP[1:0]
UR4RPTY[1:0]
DMA_LCM_CFG
FA70H
LCMIE
-
-
-
LCMIP[1:0]
LCMPTY[1:0]
M2MIP: DMA_M2M(Memory-to Memory DMA)interrupt priority control bits
00: DMA_M2M interrupt priority level is 0 (lowest level)
01: DMA_M2M interrupt priority is level 1 (lower level)
10: DMA_M2M interrupt priority is level 2 (higher level)
11: DMA_M2M interrupt priority level is 3 (the highest level)
ADCIP: DMA_ADC(ADC DMA)interrupt priority control bits
00: DMA_ADC interrupt priority level is 0 (lowest level)
01: DMA_ADC interrupt priority is level 1 (lower level)
10: DMA_ADC interrupt priority is level 2 (higher level)
11: DMA_ADC interrupt priority level is 3 (the highest level)
SPIIP: DMA_SPI(SPI DMA)interrupt priority control bits
00: DMA_SPI interrupt priority level is 0 (lowest level)
01: DMA_SPI interrupt priority is level 1 (lower level)
10: DMA_SPI interrupt priority is level 2 (higher level)
11: DMA_SPI interrupt priority level is 3 (the highest level)
UR1TIP: DMA_UR1T(UART 1 send DMA)interrupt priority control bits
00: DMA_UR1T interrupt priority level is 0 (lowest level)
01: DMA_UR1T interrupt priority is level 1 (lower level)
10: DMA_UR1T interrupt priority is level 2 (higher level)
11: DMA_UR1T interrupt priority level is 3 (the highest level)
UR1RIP: DMA_UR1R(UART 1 receive DMA)interrupt priority control bits
00: DMA_UR1R interrupt priority level is 0 (lowest level)
01: DMA_UR1R interrupt priority is level 1 (lower level)
10: DMA_UR1R interrupt priority is level 2 (higher level)
11: DMA_UR1R interrupt priority level is 3 (the highest level)
UR2TIP: DMA_UR2T(UART 2 send DMA)interrupt priority control bits
00: DMA_UR2T interrupt priority level is 0 (lowest level)
01: DMA_UR2T interrupt priority is level 1 (lower level)
10: DMA_UR2T interrupt priority is level 2 (higher level)
11: DMA_UR2T interrupt priority level is 3 (the highest level)
UR2RIP: DMA_UR2R(UART 2 receive DMA)interrupt priority control bits
00: DMA_UR2R interrupt priority level is 0 (lowest level)
01: DMA_UR2R interrupt priority is level 1 (lower level)
10: DMA_UR2R interrupt priority is level 2 (higher level)
11: DMA_UR2R interrupt priority level is 3 (the highest level)
UR3TIP: DMA_UR3T(UART 3 send DMA)interrupt priority control bits
00: DMA_UR3T interrupt priority level is 0 (lowest level)
01: DMA_UR3T interrupt priority is level 1 (lower level)
10: DMA_UR3T interrupt priority is level 2 (higher level)
11: DMA_UR3T interrupt priority level is 3 (the highest level)
UR3RIP: DMA_UR3R(UART 3 receive DMA)interrupt priority control bits
00: DMA_UR3R interrupt priority level is 0 (lowest level)
01: DMA_UR3R interrupt priority is level 1 (lower level)
10: DMA_UR3R interrupt priority is level 2 (higher level)
11: DMA_UR3R interrupt priority level is 3 (the highest level)
UR4TIP: DMA_UR4T(UART 4 send DMA)interrupt priority control bits
00: DMA_UR3R interrupt priority level is 0 (lowest level)