RM0440 Rev 4 1411/2126
RM0440 General-purpose timers (TIM15/TIM16/TIM17)
1445
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the tim_brk input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0:tim_ocx and tim_ocxn outputs are disabled or forced to idle state depending on the OSSI
bit.
1:tim_ocx and tim_ocxn outputs are enabled if their respective enable bits are set (CCxE,
CCxNE in TIM15_CCER register)
See tim_ocx/tim_ocxn enable description for more details (Section 30.7.9: TIM15
capture/compare enable register (TIM15_CCER) on page 1403).
Bit 14 AOE: Automatic output enable
0:MOE can be set only by software
1:MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIM15_BDTR register).
Bit 13 BKP: Break polarity
0: Break input tim_brk is active low
1: Break input tim_brk is active high
Note: 1: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIM15_BDTR register).
2: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (tim_brk and tim_sys_brk clock failure event) disabled
1; Break inputs (tim_brk and tim_sys_brk clock failure event) enabled
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIM15_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels that have a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See tim_ocx/tim_ocxn enable description for more details (Section 30.7.9: TIM15
capture/compare enable register (TIM15_CCER) on page 1403).
0:When inactive, tim_ocx/tim_ocxn outputs are disabled (the timer releases the output
control which is taken over by the AFIO logic, which forces a Hi-Z state)
1:When inactive, tim_ocx/tim_ocxn outputs are enabled with their inactive level as soon as
CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIM15_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See tim_ocx/tim_ocxn enable description for more details (Section 30.7.9: TIM15
capture/compare enable register (TIM15_CCER) on page 1403
).
0:When inactive, tim_ocx/tim_ocxn outputs are disabled (tim_ocx/tim_ocxn enable output
signal=0)
1:When inactive, tim_ocx/tim_ocxn outputs are forced first with their idle level as soon as
CCxE=1 or CCxNE=1. tim_ocx/tim_ocxn enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIM15_BDTR register).
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