General-purpose timers (TIM15/TIM16/TIM17) RM0440
1412/2126 RM0440 Rev 4
30.7.17 TIM15 timer deadtime register 2 (TIM15_DTR2)
Address offset: 0x054
Reset value: 0x0000 0000
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIM15_BDTR register, OISx and OISxN bits in TIM15_CR2
register and BKBID/BKE/BKP/AOE bits in TIM15_BDTR register can no longer be
written
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIM15_CCER
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
11: OCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIM15_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIM15_BDTR register
has been written, their content is frozen until the next reset.
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t
dtg
with t
dtg
=t
DTS
DTG[7:5]=10x => DT=(64+DTG[5:0])xt
dtg
with T
dtg
=2xt
DTS
DTG[7:5]=110 => DT=(32+DTG[4:0])xt
dtg
with T
dtg
=8xt
DTS
DTG[7:5]=111 => DT=(32+DTG[4:0])xt
dtg
with T
dtg
=16xt
DTS
Example if T
DTS
=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM15_BDTR register).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DTPE DTAE
rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. DTGF[7:0]
rw rw rw rw rw rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 DTPE: Deadtime preload enable
0: Deadtime value is not preloaded
1: Deadtime value preload is enabled
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM15_BDTR register).
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