RM0440 Rev 4 1421/2126
RM0440 General-purpose timers (TIM15/TIM16/TIM17)
1445
30.8 TIM16/TIM17 registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
30.8.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17)
Address offset: 0x00
Reset value: 0x0000
1514131211109876543210
Res. Res. Res.
DITH
EN
UIFRE
MAP
Res. CKD[1:0] ARPE Res. Res. Res. OPM URS UDIS CEN
rw rw rw rw rw rw rw rw rw
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 DITHEN: Dithering enable
0: Dithering disabled
1: Dithering enabled
Note: The DITHEN bit can only be modified when CEN bit is reset.
Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and
the dead-time and sampling clock (t
DTS
)used by the dead-time generators and the digital
filters (tim_tix),
00: t
DTS
=t
tim_ker_ck
01: t
DTS
=2*t
tim_ker_ck
10: t
DTS
=4*t
tim_ker_ck
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0:Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: nly counter overflow/underflow generates an update interrupt or DMA request if enabled.
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