AES hardware accelerator (AES) RM0440
1536/2126 RM0440 Rev 4
34.7.15 AES key register 6 (AES_KEYR6)
Address offset: 0x38
Reset value: 0x0000 0000
34.7.16 AES key register 7 (AES_KEYR7)
Address offset: 0x3C
Reset value: 0x0000 0000
Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They
have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used
in that case).
34.7.17 AES suspend registers (AES_SUSPxR)
Address offset: 0x040 + x * 0x4, (x = 0 to 7)
Reset value: 0x0000 0000
These registers contain the complete internal register states of the AES processor when the
AES processing of the current task is suspended to process a higher-priority task.
Upon suspend, the software reads and saves the AES_SUSPxR register contents (where x
is from 0 to 7) into memory, before using the AES processor for the higher-priority task.
Upon completion, the software restores the saved contents back into the corresponding
suspend registers, before resuming the original task.
Note: These registers are used only when GCM, GMAC, or CCM chaining mode is selected.
These registers can be read only when AES is enabled. Reading these registers while AES
is disabled returns 0x0000 0000.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[223:208]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
KEY[207:192]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 KEY[223:192]: Cryptographic key, bits [223:192]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[255:240]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
KEY[239:224]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 KEY[255:224]: Cryptographic key, bits [255:224]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
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