Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0440
1674/2126 RM0440 Rev 4
Bit 6 TC: Transmission complete
This bit indicates that the last data written in the USART_TDR has been transmitted out of
the shift register.
It is set by hardware when the transmission of a frame containing data is complete and
when TXE is set.
An interrupt is generated if TCIE=1 in the USART_CR1 register.
TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a
write to the USART_TDR register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
Bit 5 RXNE: Read data register not empty
RXNE bit is set by hardware when the content of the USART_RDR shift register has been
transferred to the USART_RDR register. It is cleared by reading from the USART_RDR
register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR
register.
An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
0: Data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the USART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line
occurs).
If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0),
whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the USART_RDR register while RXNE=1. It is cleared by a
software, writing 1 to the ORECF, in the USART_ICR register.
An interrupt is generated if RXNEIE=1 or EIE = 1 in the USART_CR1 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the USART_RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multi buffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in
the USART_CR3 register.
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