RM0440 Rev 4 2117/2126
RM0440 Revision history
2119
10-Oct-2019
2
(continued)
AES hardware accelerator (AES)
- Updated Section 34: AES hardware accelerator (AES).
USB power delivery interface (UCPD) section
– Updated Section 46: USB Type-C™ / USB Power Delivery interface (UCPD).
Debug section
– Updated Section 47.4.2: Flexible SWJ-DP pin assignment.
– Updated Section 47.8.3: SW-DP state machine (reset, idle states, ID code) ID code
by 0x2BA01477.
– Updated Table 444: Flexible TRACE pin assignment.
– Updated Table 432: JTAG debug port data registers.
06-Apr-2020 3
Added Category 4 devices (STM32G491, STM32G4A1) in:
– Table 1: STM32G4 Series memory density.
– Table 2: Product specific features.
– Section 2.4: Embedded SRAM.
– Section 2.4.1: Parity check.
– Table 4: CCM SRAM organization.
– Section 2.5: Flash memory overview.
– Section 4: Embedded Flash memory (FLASH) for category 4 devices.
– Table 90: DMAMUX instantiation.
Embedded Flash memory (FLASH) section:
Updated:
– Number of wait states according to CPU clock (HCLK) frequency tables for all
categories.
– Table 11: Option byte organization.
– Table 21: Option byte organization.
– Section 3.4.2: Option bytes programming ‘activating dual bank mode (switching from
DBANK=0 to DBANK=1)’ paragraph.
– Section 4.7.6: Flash control register (FLASH_CR) PNB[7:0] bits.
– Section 4.7.8: Flash option register (FLASH_OPTR) register description adding
PB4_PUPEN bit.
– Section 5.7.14: FLASH register map.
Power control (PWR) section:
Updated:
– Table 38: Range 1 boost mode configuration removing the lower SYSCLK limits.
– Section 6.4.2: Power control register 2 (PWR_CR2) PLS[2:0] bit description.
Reset and clock control (RCC) section:
Updated:
– Figure 17: Clock tree.
– Table 51: RCC register map and reset values.
Peripherals interconnect matrix section:
– Updated Table 60: STM32G4 Series peripherals interconnect matrix
.
Table 447. Document revision history (continued)
Date Revision Changes
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