RM0440 Rev 4 231/2126
RM0440 Power control (PWR)
271
ADC and DAC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
V
REF+
a separate reference voltage lower than V
DDA
. V
REF+
is the highest voltage,
represented by the full scale value, for an analog input (ADC) or output (DAC) signal.
V
REF+
can be provided either by an external reference of by an internal buffered voltage
reference (VREFBUF).
The internal buffered voltage reference (VREFBUF) is enabled by setting the ENVR bit in
the Section 23.4.1: VREFBUF control and status register (VREFBUF_CSR). The internal
buffered voltage reference (VREFBUF) is set to 2.048 V, 2.5 V or 2.9 V according the
VRS[1:0] bits setting. The internal buffered voltage reference can also provide the voltage to
external components through V
REF+
pin. Refer to the device datasheet and to Section 23:
Voltage reference buffer (VREFBUF) for further information.
6.1.2 USB transceivers supply
The USB transceivers are supplied from V
DD
power supply pin. V
DD
range for USB usage is
from 3.0 V to 3.6 V.
6.1.3 Battery backup domain
To retain the content of the Backup registers and supply the RTC function when V
DD
is
turned off, the VBAT
pin can be connected to an optional backup voltage supplied by a
battery or by another source.
The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing
the RTC to operate even when the main power supply is turned off. The switch to the V
BAT
supply is controlled by the power-down reset embedded in the Reset block.
Warning: During t
RSTTEMPO
(temporization at V
DD
startup) or after a PDR
has been detected, the power switch between V
BAT
and V
DD
remains connected to V
BAT
.
During the startup phase, if V
DD
is established in less than
t
RSTTEMPO
(refer to the datasheet for the value of t
RSTTEMPO
)
and V
DD
> V
BAT
+ 0.6 V, a current may be injected into V
BAT
through an internal diode connected between V
DD
and the
power switch (V
BAT
).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect V
BAT
externally to V
DD
with a 100 nF external ceramic decoupling capacitor.
When the backup domain is supplied by V
DD
(analog switch connected to V
DD
), the
following pins are available:
• PC13, PC14 and PC15, which can be used as GPIO pins
• PC13, PC14 and PC15, which can be configured by RTC or LSE (refer to Section 35.3: