Analog-to-digital converters (ADC) RM0440
652/2126 RM0440 Rev 4
DMA circular mode (DMACFG=1)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available in the data register, even if the DMA has reached the last DMA transfer. This
allows configuring the DMA in circular mode to handle a continuous analog input data
stream.
21.4.27 Dynamic low-power features
Auto-delayed conversion mode (AUTDLY)
The ADC implements an auto-delayed conversion mode controlled by the AUTDLY
configuration bit. Auto-delayed conversions are useful to simplify the software as well as to
optimize performance of an application clocked at low frequency where there would be risk
of encountering an ADC overrun.
When AUTDLY=1, a new conversion can start only if all the previous data of the same group
has been treated:
• For a regular conversion: once the ADC_DR register has been read or if the EOC bit
has been cleared (see Figure 120).
• For an injected conversion: when the JEOS bit has been cleared (see Figure 121).
This is a way to automatically adapt the speed of the ADC to the speed of the system which
will read the data.
The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after
each sequence of injected conversions (whatever JDISCEN=0 or 1).
Note: There is no delay inserted between each conversions of the injected sequence, except after
the last one.
During a conversion, a hardware trigger event (for the same group of conversions) occurring
during this delay is ignored.
Note: This is not true for software triggers where it remains possible during this delay to set the
bits ADSTART or JADSTART to restart a conversion: it is up to the software to read the data
before launching a new conversion.
No delay is inserted between conversions of different groups (a regular conversion followed
by an injected conversion or conversely):
• If an injected trigger occurs during the automatic delay of a regular conversion, the
injected conversion starts immediately (see Figure 121).
• Once the injected sequence is complete, the ADC waits for the delay (if not ended) of
the previous regular conversion before launching a new regular conversion (see
Figure 123).
The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular
conversion can start only when the automatic delay of the previous injected sequence of
conversion has ended (when JEOS has been cleared). This is to ensure that the software
can read all the data of a given sequence before starting a new sequence (see Figure 124).
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