STC micro STC8A8K64D4 Series - Page 226

STC8A8K64D4 Series Manual
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- 210 -
0: disable comparator falling-edge interrupt.
1: enable comparator falling-edge interrupt.
Enhanced PWM Configuration Register
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
PWMCFG
F6H
-
-
-
-
PWMCBIF
EPWMCBI
ENPWMTA
PWMCEN
EPWMCBI: Enhanced PWM0 counter interrupt enable bit.
0: disable PWM0 counter interrupt
1: enable PWM0 counter interrupt
Enhanced PWM Abnormal Detection Control Register
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
PWMFDCR
FF06H
INVCMP
INVIO
ENFD
FLTFLIO
EFDI
FDCMP
FDIO
FDIF
EFDI: PWM external abnormal event interrupt enable bit.
0: disable PWM external abnormal event interrupt
1: enable PWM external abnormal event interrupt
Enhanced PWM Control Register
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
PWM0CR
FF14H
ENO
INI
-
PWM0PS[1:0]
ENI
ENT2I
ENT1I
PWM1CR
FF1CH
ENO
INI
-
PWMPS[1:0]
ENI
ENT2I
ENT1I
PWM2CR
FF24H
ENO
INI
-
PWM2PS[1:0]
ENI
ENT2I
ENT1I
PWM3CR
FF2CH
ENO
INI
-
PWM3PS[1:0]
ENI
ENT2I
ENT1I
PWM4CR
FF34H
ENO
INI
-
PWM4PS[1:0]
ENI
ENT2I
ENT1I
PWM5CR
FF3CH
ENO
INI
-
PWM5PS[1:0]
ENI
ENT2I
ENT1I
PWM6CR
FF44H
ENO
INI
-
PWM6PS[1:0]
ENI
ENT2I
ENT1I
PWM7CR
FF4CH
ENO
INI
-
PWM7PS[1:0]
ENI
ENT2I
ENT1I
ENI: PWM channel interrupt enable bit.
0: disable PWM interrupt
1: enable PWM interrupt
ENT2SI: PWM channel 2nd trigger point interrupt enable bit.
0: disable the 2nd trigger point interrupt of PWM
1: enable the 2nd trigger point interrupt of PWM
ENT1SI: PWM channel 1st trigger point interrupt enable bit.
0: disable the 1st trigger point interrupt of PWM
1: enable the 1st trigger point interrupt of PWM
I2C Control Registers
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
I2CMSCR
FE81H
EMSI
-
-
-
MSCMD[3:0]
I2CSLCR
FE83H
-
ESTAI
ERXI
ETXI
ESTOI
-
-
SLRST
EMSI: I
2
C master mode interrupt enable bit.
0: disable I
2
C master mode interrupt.
1: enable I
2
C master mode interrupt.
ESTAI: I
2
C slave receives the START event interrupt enable bit.
0: disable I
2
C slave receives the START event interrupt.
1: enable I
2
C slave receives the START event interrupt.
ERXI: I
2
C slave completes receiving data event interrupt enable bit.
0: disable I
2
C slave completes receiving data event interrupt.
1: enable I
2
C slave completes receiving data event interrupt.
ETXI: I
2
C slave completes transmitting data event interrupt enable bit.
0: disable I
2
C slave completes transmitting data event interrupt.
1: enable I
2
C slave completes transmitting data event interrupt.
ESTOI: I
2
C slave receives STOP event interrupt enable bit.
0: disable I
2
C slave receives STOP event interrupt.
1: enable I
2
C slave receives STOP event interrupt.
Port interrupt enable registers