The 3 Custom Chips
The 3 custom chips provide very fast manipulation
of
graphics and audio data
in
the display RAM. All the major functions
in
the chips are DMA driven; that is,
streams
of
data are moved between the custom chips and display RAM under
DMA control. These streams
of
data are acted upon by the custom chips. Fat
Agnus, custom chip
#1,
contains
25
dedicated purpose DMA counters.
The 3 chips have control registers which are usually loaded by the 68000.
However, Fat Agnus also has the capability
of
loading control registers
in
the
other 2 custom chips. When Fat Agnus performs a bus cycle, it outputs a code on
the Register Address Bus telling the other 2 chips the nature
of
the bus cycle.
This
is
necessary because many
of
the bus cycles provide data to or from the
other 2 chips, thus they must cooperate appropriately.
In
addition to manipulating data
in
the display RAM, the custom chips output
streams
of
data to the video output circuits and audio output circuits, and they
move data
to
and from the floppy disks and serial port.
Note that the display RAM buses can be completely isolated from the 68000
buses by Fat Agnus and Data Bus drivers. Thus, Fat Agnus can be performing a
bus cycle on the display buses simultaneously with the 68000 performing a bus
cycle on its buses. This parallelism increases throughout.
Bus Control, Address/Data MUX, Address Driver
The bus control logic resides
in
the control chip (GARY) and Fat Agnus. They
provide 3 major functions, they:
Synchronize the 68000 to the current phase
of
CI
Arbitrate between the 68000 and Fat Agnus for the
di
splay buses
Generate DRAM timing for the video RAM bus drivers appropriate
to
the
current cycle
Synchronizing the 68000
to
CI
is
straightforward, since the 68000
is
clocked by
7M which
is
twice the frequency and synchronous to C 1.
If
the 68000 starts a bus
cycle in the wrong phase
of
C I, the bus control chip merely delays I
DT
ACK long
enough so that the 68000 will complete the bus cycle
in
the desired phase
relationship to C
1.
This phase relationship
is
necessary because the custom chips
and the display RAM are clocked by C 1 .
A-
14
Technical Reference
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