RM0440 Rev 4 321/2126
RM0440 Reset and clock control (RCC)
338
7.4.22 AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR)
Address offset: 0x70
Reset value: 0x0000 0101
Access: no wait state, word, half-word and byte access
7.4.23 APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1)
Address: 0x78
Reset value: 0xD2FE CD3F
Access: no wait state, word, half-word and byte access
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. QSPISMEN Res. Res. Res. Res. Res. Res. Res.
FMC
SMEN
rw rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPISMEN: QUADSPI memory interface clock enable during Sleep and Stop modes
Set and cleared by software.
0: QUADSPI clock disabled by the clock gating
(1)
during Sleep and Stop modes
1: QUADSPI clock enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCSMEN: Flexible static memory controller clocks enable during Sleep and Stop modes
Set and cleared by software.
0: FSMC clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: FSMC clocks enabled by the clock gating
(1)
during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
SMEN
I2C3
SMEN
Res.
PWR
SMEN
Res. Res.
FDCAN
SMEN
Res.
USB
SMEN
I2C2
SMEN
I2C1
SMEN
UART5
SMEN
UART4
SMEN
USART
3SMEN
USART
2SMEN
Res.
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
SMEN
SPI2
SMEN
Res. Res.
WWDG
SMEN
RTCAPB
SMEN
Res.
CRS
SMEN
Res. Res.
TIM7
SMEN
TIM6
SMEN
TIM5
SMEN
TIM4
SMEN
TIM3
SMEN
TIM2
SMEN
rw rw rw rw rw rw rw rw rw rw rw
To Next Page
Loading...
Need help?
General
