ST STM32G473 User Manual

Reset and clock control (RCC) RM0440
322/2126 RM0440 Rev 4
Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPTIM1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: LPTIM1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 30 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: I2C3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 29 Reserved, must be kept at reset value.
Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Power interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: Power interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 27:26 Reserved, must be kept at reset value.
Bit 25 FDCANSMEN: FDCAN clocks enable during Sleep and Stop modes
Set and cleared by software.
0: FDCAN clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: FDCAN clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 24 Reserved, must be kept at reset value.
Bit 23 USBSMEN: USB device clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USB device clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USB device clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 22 I2C2SMEN: I2C2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: I2C2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 21 I2C1SMEN: I2C1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: I2C1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 20 UART5SMEN: UART5 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART5 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: UART5 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART4 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: UART4 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 18 USART3SMEN: USART3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USART3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English