ST STM32G473 User Manual

Reset and clock control (RCC) RM0440
324/2126 RM0440 Rev 4
7.4.24 APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2)
Address offset: 0x7C
Reset value: 0x0000 0103
Access: no wait state, word, half-word and byte access
Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 7654321 0
Res. Res. Res. Res. Res. Res. Res.
UCPD1
SMEN
Res. Res. Res. Res. Res. Res.
I2C4
SMEN
LP
UART1
SMEN
rw rw rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 UCPD1SMEN: UCPD1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UCPD1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: UCPD1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 I2C4SMEN: I2C4 clocks enable during Sleep and Stop modes
Set and cleared by software
0: I2C4 clocks disabled by the clock gating
(2)
during Sleep and Stop modes
1: I2C4 clock enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPUART1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: LPUART1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
2. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English