•
MLPPP is only supported on serial PPP interfaces. MLPPP is not supported over Frame Relay, ATM,
or PPPoE interfaces.
•
On a 2-Port and 4-Port Channelized T3 SPA, when one of the T3 ports is configured as a DS3
Clear-Channel interface and the other T3 ports are configured with a large number (greater than or equal
to 400) of low bandwidth channels (NxDS0, N=1, 2, 3, or 4), the DS3 Clear-Channel interface is not
able to run at 100 percent DS3 line rate when the low bandwidth channels are idle (when not transmitting
or receiving packets). This issue does not occur if the low bandwidth channels are not idle.
•
The maximum number of channels supported on the channelized SPAs are:
◦ 1023 channels per SPA—On a 2-Port and 4-Port Channelized T3 SPA or 1-Port Channelized
OC-3/STM-1 SPA.
◦ 2000 NxDS0 per SPA—On a 1-Port Channelized OC-12/STM-4 SPA.
•
On a 2-Port and 4-Port Channelized T3 SPA or 1-Port Channelized OC-3/STM-1 SPA, the maximum
number of FIFO buffers is 4096. The FIFO buffers are shared among the interfaces; how they are shared
is determined by speed. If all the FIFO buffers have been assigned to existing interfaces, a new interface
cannot be created, and the “%Insufficient FIFOs to create channel group” error message is seen.
To find the number of available FIFO buffers, use the show controller t3 command:
Router# show controller t3 1/0/0
T3 1/0/0 is up.
Hardware is SPA-4XCT3/DS0
IO FPGA version: 2.6, HDLC Framer version: 0
T3/T1 Framer(1) version: 2, T3/T1 Framer(2) version: 2
SUBRATE FPGA version: 1.4
HDLC controller available FIFO buffers 3112
The following table provides information about FIFO allocation.
Table 23: FIFO Allocation
Number of FIFO BuffersNumber of Time Slots
4
1–6 DS0
6
7–8 DS0
69 DS0
8
10–12 DS0
12
13–23 DS0
4
1–6 E1 TS
6
7–9 E1 TS
8
11–16 E1 TS
16
17–31 E1 TS
Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Software Configuration Guide, Cisco IOS
XE Everest 16.5
216 OL-14127-17
Overview of the Serial SPAs
Restrictions
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