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Fujitsu PRIMERGY TX2550 M5 - Page 395

Fujitsu PRIMERGY TX2550 M5
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Six channel DDR4 memory architecture (per CPU), 2 DIMMs per channel
12 memory DIMM sockets R3 (6 per CPU)
Supports RDIMM w/ ECC, LRDIMM, 3DS-LRDIMM and NVM/LRDIMM
Supports DDR4 up to 2933 MT/s
Supports NVM/LRDIMM up to 2666 MT/s
Up to 3TB/CPU using DDR4 DIMM (256 GB modules)
Up to 4TB/CPU using NVM/LRDIMM + DDR4
Error detection and correction (ECC)
Lockstep mode is not supported by BIOS on this platform
SDDC (single device data correction) for all single x4 DIMM failures
x8 DIMM SDDC requires lockstep mode, but lockstep mode is not
supported
Channel mirroring within a CPU socket
Hardware memory scrubbing
Rank level sparing
The notation of the CPU, memory channels and DIMM sockets correspond to
the silk print on the system board.
On second CPU the memory channels are named G, H, J, K, L and M and
placed accordingly
.
Figure 256: Memory slots of CPU 1
Main memory
TX2550 M5 Upgrade and Maintenance Manual 395

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