Siemens SIMATIC S7-1200 - Page 581

Technology instructions
10.1 Counting (High-speed counters)
S7-1200 Programmable controller
System Manual, V4.2, 09/2016, A5E02486680-AK
581
Use the following table and ensure that the CPU and SB input channels that you connect
can support the maximum pulse rates in your process signals:
Table 10- 9 CPU input: maximum frequency
CPU
CPU Input channel
Operating phase: Single
phase or Two phase
Operating phase: A/B
counter or A/B Counter
fourfold
1211C
Ia.0 to Ia.5
100 kHz
80 kHz
1212C Ia.0 to Ia.5 100 kHz 80 kHz
Ia.6, Ia.7
30 kHz
20 kHz
1214C and 1215C
Ia.0 to Ia.5
100kHz
80kHz
Ia.6 to Ib.5
30 kHz
20 kHz
1217C
Ia.0 to Ia.5
100 kHz
80 kHz
Ia.6 to Ib.1
30 kHz
20 kHz
Ib.2 to Ib.5
(.2+, .2- to .5+, .5-)
1 MHz 1 MHz
Table 10- 10 SB signal board input: maximum frequency (optional board)
SB signal board
SB input channel
Operating phase: Single
phase or Two phase
Operating phase: A/B
counter or A/B Counter
fourfold
SB 1221, 200 kHz
Ie.0 to Ie.3
200kHz
160 kHz
SB 1223, 200 kHz
Ie.0, Ie.1
200kHz
160 kHz
SB 1223
Ie.0, Ie.1
30 kHz
20 kHz
When assigning an input point to an HSC function, you can assign the same input point to
multiple HSC functions. For example, assigning I0.3 to the Sync input of HSC1 and the Sync
input of HSC2 to synchronize the count of both HSCs at the same time is a valid
configuration; however, it generates a compiler warning.