Technology instructions
10.1 Counting (High-speed counters)
S7-1200 Programmable controller
586 System Manual, V4.2, 09/2016, A5E02486680-AK
Table 10- 14 Execution condition codes
80A1 HSC identifier does not address a HSC
80B2 Illegal value in NEW_CV
Illegal value in NEW_PERIOD
Multiple access to the high-speed counter
High-speed counter (HSC) not enabled in CPU hardware configuration
The CTRL_HSC instruction is typically placed in a hardware interrupt OB that is executed
when the counter hardware interrupt event is triggered. For example, if a CV=RV event
triggers the counter interrupt, then a hardware interrupt OB code block executes the
CTRL_HSC instruction and can change the reference value by loading a NEW_RV value.
The current count value is not available in the CTRL_HSC parameters. The process image
address that stores the current count value is assigned during the hardware configuration of
the high-speed counter. You may use program logic to directly read the count value. The
value returned to your program will be a correct count for the instant in which the counter
was read. The counter will continue to count high-speed events. Therefore, the actual count
value could change before your program completes a process using an old count value.
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