RM0440 Rev 4 111/2126
RM0440 Embedded Flash memory (FLASH) for category 3 devices
228
PCROP1 Start address option bytes
Flash memory address: 0x1FFF 7808
ST production value: 0xFFFF FFFF
PCROP1 End address option bytes
Flash memory address: 0x1FFF 7810
ST production value: 0x00FF 0000
Bit 11 Reserved, must be kept at reset value.
Bits10:8 BOR_LEV: BOR reset Level
These bits contain the VDD supply level threshold that activates/releases the
reset.
000: BOR Level 0. Reset level threshold is around 1.7 V
001: BOR Level 1. Reset level threshold is around 2.0 V
010: BOR Level 2. Reset level threshold is around 2.2 V
011: BOR Level 3. Reset level threshold is around 2.5 V
100: BOR Level 4. Reset level threshold is around 2.8 V
Bits 7:0 RDP: Read protection level
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. PCROP1_STRT[14:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:0 PCROP1_STRT: PCROP area start offset
DBANK=1
PCROP1_STRT contains the first double-word of the PCROP area for bank1.
DBANK=0
PCROP1_STRT contains the first 2xdouble-word of the PCROP area for all
memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP
_RDP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PCROP1_END[14:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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