RM0440 Rev 4 1179/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
1226
Bits 25, 6:4 MMS[3:0]: Master mode selection
These bits select the information to be sent in master mode to slave timers for
synchronization (tim_trgo). The combination is as follows:
0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If
the reset is generated by the trigger input (slave mode controller configured in reset
mode) then the signal on tim_trgo is delayed compared to the actual reset.
0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is
useful to start several timers at the same time or to control a window in which a slave
timer is enable. The Counter Enable signal is generated by a logic AND between CEN
control bit and the trigger input when configured in gated mode. When the Counter
Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if
the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
0010: Update - The update event is selected as trigger output (tim_trgo). For instance a
master timer can then be used as a prescaler for a slave timer.
0011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to
be set (even if it was already high), as soon as a capture or a compare match
occurred. (tim_trgo).
0100: Compare - tim_oc1refc signal is used as trigger output (tim_trgo)
0101: Compare - tim_oc2refc signal is used as trigger output (tim_trgo)
0110: Compare - tim_oc3refc signal is used as trigger output (tim_trgo)
0111: Compare - tim_oc4refc signal is used as trigger output (tim_trgo)
1000: Encoder Clock output - The encoder clock signal is used as trigger output
(tim_trgo). This code is valid for the following SMS[3:0] values: 0001, 0010, 0011,
1010, 1011, 1100, 1101, 1110, 1111. Any other SMS[3:0] code is not allowed and may
lead to unexpected behavior.
Other codes reserved
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0:When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only
1:When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on tim_trgi
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0:CCxE, CCxNE and OCxM bits are not preloaded
1:CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when a commutation event (COM) occurs (COMG bit set or rising edge detected on
tim_trgi, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.
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