USB Type-C™ / USB Power Delivery interface (UCPD) RM0440
2056/2126 RM0440 Rev 4
If dead battery behavior is not required (for example for source only products), then
UCPDx_DBCC1 and UCPDx_DBCC2 pins must both be tied to ground. After power arrives
and the MCU boots, the desired behavior in this case (for example source) must be
programmed into ANAMODE and ANASUBMODE[1:0] before setting the UCPD_DBDIS bit
of the PWR_CR3 register to remove dead battery Rd default behavior and allow the values
just programmed to take effect.
Use of Standby low-power mode is possible for sinks in the unattached state.
46.4.7 UCPD Type-C voltage monitoring and de-bouncing
For correct operation of the Type-C state machine and for detecting the cable orientation,
the CC1/2 lines must be monitored for voltage level, while ignoring fast events such as
peaks.
Thresholds between voltage levels on the CC1/2 lines are determined through PHY
threshold detector settings.
The TYPEC_VSTATE_CC1/2[1:0] bitfields reflect the CC1/2 line levels processed with a
hardware de-bouncing filter that suppresses high-speed line events such as peaks. The
PHYCCSEL bit selects the line, CC1 or CC2, to be used for Power Delivery signaling.
For minimizing the power consumption, it is recommended to use the polling method, with
the Type-C detectors only turned on for the instant of polling, rather than keeping the
Type-C detectors permanently on and wake the device up from Stop mode upon CC1/2 line
events.
46.4.8 UCPD fast role swap (FRS) signaling and detection
FRS signaling
The FRS condition (a pulse of a specific length), is generated upon setting the FRSTX bit.
For the duration of FRS condition, the I/O configured as UCPD_FRSTX (alternate function)
controls, with high level, the gate of an external NMOS transistor that pulls the active CC
line down.
FRS detection
FRS monitoring is enabled by setting the bit FRSRXEN, after writing PHYCCSEL that
selects the active CC line depending on the cable orientation detected.
46.4.9 UCPD DMA Interface
DMA is implemented in the UCPD and when it is enabled the byte-level interrupts to handle
USBPD1_TXDR and USBPD1_RXDR registers (Tx and Rx data register, each one byte)
are no longer needed.
By enabling bits TXDMAEN and/or RXDMAEN, DMA can be activated independently for Tx
and/or Rx functionality.
46.4.10 Wakeup from Stop mode
For power consumption optimization, it is useful to use Stop mode and wait for events on
CC lines to wake the MCU up.
In order for this to work, it must be first enabled by writing a 1 to WUPEN.
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