Power control (PWR) RM0440
238/2126 RM0440 Rev 4
6.3 Low-power modes
By default, the microcontroller is in Run mode after a system or a power Reset. Several
low-power modes are available to save power when the CPU does not need to be kept
running, for example when waiting for an external event. It is up to the user to select the
mode that gives the best compromise between low-power consumption, short startup time
and available wakeup sources.
The device features seven low-power modes:
• Sleep mode: CPU clock off, all peripherals including Cortex
®
-M4 with FPU core
peripherals such as NVIC, SysTick, etc. can run and wake up the CPU when an
interrupt or an event occurs. Refer to Section 6.3.4: Sleep mode.
• Low-power run mode: This mode is achieved when the CPU clock frequency is
reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The
regulator is in low-power mode to minimize the regulator's operating current. Refer to
Section 6.3.2: Low-power run mode (LP run).
• Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex
®
-
M4 with FPU is off. Refer to Section 6.3.5: Low-power sleep mode (LP sleep).
• Stop 0 and Stop 1 modes: SRAM and all registers content are retained. All clocks in the
V
CORE
domain are stopped, the PLL, the HSI16 and the HSE are disabled. The LSI
and the LSE can be kept running.
The RTC and TAMP can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop
mode to detect their wakeup condition.
In Stop 0 mode, the main regulator remain ON, which allows the fastest wakeup time
but with higher consumption. The active peripherals and the wakeup sources are the
same as in Stop 1 mode.
The system clock, when exiting from Stop 0 or Stop 1 mode, is the HSI16 clock. If the
device is configured to wake up in low-power run mode, the HPRE bits in RCC_CFGR
register must be configured prior to entering Stop mode to provide a frequency not
greater than 2 MHz.
Refer to Section 6.3.6: Stop 0 mode for details on Stop 0 mode.
• Standby mode: V
CORE
domain is powered off. However, it is possible to preserve the
SRAM contents:
– Standby mode with SRAM2 retention when the bit RRS is set in PWR_CR3
register. In this case, SRAM2 is supplied by the low-power regulator.
– Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the
main regulator and the low-power regulator are powered off.
All clocks in the V
CORE
domain are stopped, the PLL, the HSI16 and the HSE oscillator
are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The system clock, when exiting Standby modes, is the HSI16 oscillator clock.
Refer to Section 6.3.8: Standby mode.
• Shutdown mode: V
CORE
domain is powered off. All clocks in the V
CORE
domain are
stopped, the PLL, the HSI16, the LSI and the HSE are disabled. The LSE can be kept
running. The system clock, when exiting the Shutdown mode, is HSI16 oscillator clock.
In this mode, the supply voltage monitoring is disabled and the product behavior is not
guaranteed in case of a power voltage drop. Refer to Section 6.3.9: Shutdown mode.
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