ST STM32G473 User Manual

Reset and clock control (RCC) RM0440
306/2126 RM0440 Rev 4
7.4.12 APB1 peripheral reset register 2 (RCC_APB1RSTR2)
Address offset: 0x3C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
7.4.13 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res.
UCPD1
RST
Res. Res. Res. Res. Res. Res.
I2C4
RST
LP
UART1
RST
rw rw rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 UCPD1RST: UCPD1 reset
Set and cleared by software.
0: No effect
1: Reset UCPD1
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 I2C4RST: I2C4 reset
Set and cleared by software
0: No effect
1: Reset I2C4
Bit 0 LPUART1RST: Low-power UART 1 reset
Set and cleared by software.
0: No effect
1: Reset LPUART1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
HRTIM1
RST
Res. Res. Res. Res.
SAI1
RST
TIM20
RST
Res.
TIM17
RST
TIM16
RST
TIM15R
ST
rw rw rw rw rw rw
1514131211 10 9876 5 4 3 2 1 0
SPI4
RST
USART1
RST
TIM8
RST
SPI1
RST
TIM1
RST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SYS
CFG
RST
rw rw rw rw rw rw

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English