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Digital-to-analog converter (DAC) RM0440

738/2126 RM0440 Rev 4

22.4.8 DMA requests

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC

channel DMA requests.

When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the

value of the DAC_DHRx register is transferred into the DAC_DORx register when the

transfer is complete, and a DMA request is generated.

In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one

DMA request is needed, only the corresponding DMAENx bit must be set. In this way, the

application can manage both DAC channels in dual mode by using one DMA request and a

unique DMA channel.

As DAC_DHRx to DAC_DORx data transfer occurred before the DMA request, the very first

data has to be written to the DAC_DHRx before the first trigger event occurs.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the

acknowledgment for the first external trigger is received (first request), then no new request

is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set,

reporting the error condition. The DAC channelx continues to convert old data.

The software must clear the DMAUDRx flag by writing 1, clear the DMAEN bit of the used

DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly.

The software must modify the DAC trigger conversion frequency or lighten the DMA

workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by

enabling both DMA data transfer and conversion trigger.

For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit

in the DAC_CR register is enabled.

DMA Double data mode

When the DMA controller is used in Normal mode, only 12-bit (or 8-bit) data are transferred

by a DMA request. As the AHB width is 32 bits, two 12-bit data may be transferred

simultaneously. To use this mode, set the DMADOUBLEx bit of DAC_MCR register.

A DAC DMA request is generated every two external triggers (except for software triggers)

when the DMAENx bit is set:

1. When the first trigger is detected, the value of the DAC_DHRx and DAC_DHRBx

registers are transferred into the DAC_DORx and DAC_DORBx registers. The actual

DAC data is loaded into the DAC_DORx register. A DMA request is then generated.

The DMA writes the new data to the DAC_DHRx and DAC_DHRBx data registers.

2. When the next trigger is detected, the actual DAC data is loaded into the DAC_DHRBx

indicates which DOR data is actually loaded into the analog DAC input.

DMA underrun function is also supported in DMA Double data mode.

In DMA Double mode, DMA requests can only handle one DAC channel. To use two

channel outputs in DMA Double mode, each DMA channel has to be configured separately.

ST STM32G473 User Manual

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