Digital-to-analog converter (DAC) RM0440
762/2126 RM0440 Rev 4
22.7.12 DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
22.7.13 DAC channel2 data output register (DAC_DOR2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. DACC1DORB[11:0]
rrrrrrrrrrrr
1514131211109876543210
Res. Res. Res. Res. DACC1DOR[11:0]
rrrrrrrrrrrr
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC1DORB[11:0]: DAC channel1 data output
These bits are read-only. They contain data output for DAC channel1 B.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. DACC2DORB[11:0]
rrrrrrrrrrrr
1514131211109876543210
Res. Res. Res. Res. DACC2DOR[11:0]
rrrrrrrrrrrr
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC2DORB[11:0]: DAC channel2 data output
These bits are read-only. They contain data output for DAC channel2 B.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read-only, they contain data output for DAC channel2.
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