High-resolution timer (HRTIM) RM0440
846/2126 RM0440 Rev 4
27.3 Functional description
27.3.1 General description
The HRTIM can be partitioned into several sub entities:
• The master timer
• The timing units (timer A to timer F)
• The output stage
• The burst mode controller
• An external event and fault signal conditioning logic that is shared by all timers
• The system interface
The master timer is based on a 16-bit up counter. It can set/reset any of the 12 outputs via 4
compare units and it provides synchronization signals to the 6 timer units. Its main purpose
is to have the timer units controlled by a unique source. An interleaved buck converter is a
typical application example where the master timer manages the phase-shifts between the
multiple units.
The timer units are working either independently or coupled with the other timers including
the master timer. Each timer contains the controls for two outputs. The outputs set/reset
events are triggered either by the timing units compare registers or by events coming from
the master timer, from the other timers or from external events.
The output stage has several duties
• Addition of deadtime when the 2 outputs are configured in complementary PWM mode
• Addition of a carrier frequency on top of the modulating signal
• Management of fault events, by asynchronously asserting the outputs to a predefined
safe level
The burst mode controller can take over the control of one or multiple timers in case of light-
load operation. The burst length and period can be programmed, as well as the idle state of
the outputs.
The external event and fault signal conditioning logic includes:
• The input selection MUXes (for instance for selecting a digital input or an on-chip
source for a given external event channel)
• Polarity and edge-sensitivity programming
• Digital filtering (for 5 channels out of 12)
The system interface allows the HRTIM to interact with the rest of the MCU:
• Interrupt requests to the CPU
• DMA controller for automatic accesses to/from the memories, including an HRTIM
specific burst mode
• Triggers for the ADC and DAC converters
The HRTIM registers are split into 8 groups:
• Master timer registers
• Timer A to timer F registers
• Common registers for features shared by all timer units
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