High-resolution timer (HRTIM) RM0440
858/2126 RM0440 Rev 4
Roll-over event
A counter roll-over event is generated when the counter goes back to 0 after having reached
the period value set in the HRTIM_PERxR register in continuous mode.
This event is used for multiple purposes in the HRTIM:
– To set/reset the outputs
– To trigger the register content update (transfer from preload to active)
– To trigger an IRQ or a DMA request
– To serve as a burst mode clock source or a burst start trigger
– As an ADC trigger
– To decrement the repetition counter
If the initial counter value is above the period value when the timer is started, or if a new
period is set while the counter is already above this value, the counter is not reset: it
overflows at the maximum period value and the repetition counter does not decrement.
Timer reset
The reset of the timing unit counter can be triggered by up to 30 events that can be selected
simultaneously in the HRTIM_RSTxR register, among the following sources:
– The timing unit: compare 2, compare 4 and update (3 events)
– The master timer: reset and compare 1..4 (5 events)
– The external events EXTEVNT1..10 (10 events)
– All other timing units (e.g. timer B..F for timer A): compare 1, 2 and 4 (12 events)
Several events can be selected simultaneously to handle multiple reset sources. In this
case, the multiple reset requests are ORed. When 2 counter reset events are generated
within the same f
HRTIM
clock cycle, the last counter reset is taken into account.
Additionally, it is possible to do a software reset of the counter using the TxRST bits in the
HRTIM_CR2 register. These control bits are grouped into a single register to allow the
simultaneous reset of several counters.
The reset requests are taken into account only once the related counters are enabled
(TxCEN bit set).
When the f
HRTIM
clock prescaling ratio is above 32 (counting period above f
HRTIM
), the
counter reset event is delayed to the next active edge of the prescaled clock. This allows to
maintain a jitterless waveform generation when an output transition is synchronized to the
reset event (typically a constant Ton time converter).
Figure 187 shows how the reset is handled for a clock prescaling ratio of 128 (f
HRTIM
divided
by 4).
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