RM0440 Rev 4 869/2126
RM0440 High-resolution timer (HRTIM)
1083
A delayed compare is used for the output reset: the compare event can be generated only if
a capture event has occurred. No event is generated when the counter matches the delayed
compare value (counter = 4). Once the capture event has been triggered by the external
event, the content of the capture register is summed to the delayed compare value to have
the new compare value. In the example, the auto-delayed value 4 is summed to the capture
equal to 7 to give a value of 12 in the auto-delayed compare register. From this time on, the
compare event can be generated and happens when the counter is equal to 12, causing the
output to be reset.
Overcapture management in auto-delayed mode
Overcapture is prevented when the auto-delayed mode is enabled (DELCMPx[1:0] = 01, 10,
11).
When multiple capture requests occur within the same counting period, only the first capture
is taken into account to compute the auto-delayed compare value. A new capture is possible
only:
• Once the auto-delayed compare has matched the counter value (compare event)
• Once the counter has rolled over (period)
• Once the timer has been reset
Changing auto-delayed compare values
When the auto-delayed compare value is preloaded (PREEN bit set), the new compare
value is taken into account on the next coming update event (for instance on the period
event), regardless of when the compare register was written and if the capture occurred
(see Figure 193, where the delay is changed when the counter rolls over).
When the preload is disabled (PREEN bit reset), the new compare value is taken into
account immediately, even if it is modified after the capture event has occurred, as per the
example below:
1. At t1, DELCMP2 = 1.
2. At t2, CMP2_act = 0x40 => comparison disabled
3. At t3, a capture event occurs capturing the value CPTR1 = 0x20. => comparison
enabled, compare value = 0x60
4. At t4, CMP2_act = 0x100 (before the counter reached value CPTR1 + 0x40) =>
comparison still enabled, new compare value = 0x120
5. At t5, the counter reaches the period value => comparison disabled, cmp2_act = 0x100
Similarly, if the CMP1(CMP3) value changes while DELCMPx = 10 or 11, and preload is
disabled:
1. At t1, DELCMP2 = 2.
2. At t2, CMP2_act = 0x40 => comparison disabled
3. At t3, CMP3 event occurs - CMP3_act = 0x50 before capture 1 event occurs =>
comparison enabled, compare value = 0x90
4. At t4, CMP3_act = 0x100 (before the counter reached value 0x90) => comparison still
enabled, compare 2 event occurs at = 0x140
Triggered-half mode
The purpose of this mode is to allow the synchronization of 2 interleaved converters that
have variable frequency operation and require a 180° phase-shift. The basic principle is to
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