High-resolution timer (HRTIM) RM0440
904/2126 RM0440 Rev 4
while the IPPSTAT flag indicates during which period the external event occurred, to
determine the sequence of shorten pulses (A1 then A2 or vice versa).
The timer operation is not interrupted (the counter continues to run).
To enable the balanced idle mode, it is necessary to have the following initialization:
– timer operating in continuous mode (CONT = 1)
– Push-pull mode enabled
– HRTIM_CMP4xR must be set to 0 and the content transferred into the active
register (for instance by forcing a software update)
– DELCMP4[1:0] bit field must be set to 00 (auto-delayed mode disabled)
– DLYPRT[2:0] = x11 (delayed protection enable)
Note: The HRTIM_CMP4xR register must not be written during a balanced idle operation. The
CMP4 event is reserved and cannot be used for another purpose.
In balanced idle mode, it is recommended to avoid multiple external events or software-
based reset events causing an output reset. If such an event arrives before a balanced idle
request within the same period, it causes the output pulses to be unbalanced (1st pulse
length defined by the external event or software reset, while the 2nd pulse is defined by the
balanced idle mode entry).
The minimum pulsewidth that can be handled in balanced idle mode is 4 f
HRTIM
clock
periods (0x80 when CKPSC[2:0] = 0, 0x40 if CKPSC[2:0] = 1, 0x20 if CKPSC[2:0] = 2,...).
If the capture occurs before the counter has reached this minimum value, the current pulse
is extended up to 4 f
HRTIM
clock periods before being copied into the secondary output. In
any case, the pulsewidths are always balanced.
Tx1OEN and Tx2OEN bits are not affected by the balanced idle entry. To exit from balanced
idle and resume the operation, it is necessary to overwrite Tx1OEN and Tx2OEN bits to 1
simultaneously. The output state changes on the first active transition following the output
enable.
It is possible to resume operation similarly to the delayed idle entry. For instance, if the
external event arrives while output 1 is active (delayed idle effective after output 2 pulse),
the re-start sequence can be initiated for output 1 first. To do so, it is necessary to poll
CPPSTAT bit in the HRTIM_TIMxISR register. Using the above example (IPPSTAT flag
equal to 0), the operation is resumed when CPPSTAT bit is 0.
In order to have a specific re-start sequence, it is possible to poll the CPPSTAT to know
which output is active first. This allows, for instance, to re-start with the same sequence as
the idle entry sequence: if the external event arrives during output 1 active, the re-start
sequence is initiated when the output 1 is active (CPPSTAT = 0).
Note: The balanced idle mode must not be disabled while a pulse balancing sequence is on-
going. It is necessary to wait until the CMP4 flag is set, thus indicating that the sequence is
completed, to reset the DLYPRTEN bit.
The balanced idle protection mode can be triggered only when the counter is enabled
(TxCEN bit set). It remains active even if the TxCEN bit is reset, until TxyOEN bits are set.
Balanced idle can be used together with the burst mode under the following conditions:
• TxBM bit must be reset (counter clock maintained during the burst, see
Section 27.3.15),
• No balanced idle protection must be triggered while the outputs are in a burst idle state.
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