High-resolution timer (HRTIM) RM0440
982/2126 RM0440 Rev 4
27.5.16 HRTIM timer x counter register (HRTIM_CNTxR) (x = A to F)
Address offset: Block A: 0x090
Address offset: Block B: 0x110
Address offset: Block C: 0x190
Address offset: Block D: 0x210
Address offset: Block E: 0x290
Address offset: Block F: 0x310
Reset value: 0x0000 0000
27.5.17 HRTIM timer x period register (HRTIM_PERxR) (x = A to F)
Address offset: Block A: 0x094
Address offset: Block B: 0x114
Address offset: Block C: 0x194
Address offset: Block D: 0x214
Address offset: Block E: 0x294
Address offset: Block F: 0x314
Reset value: 0x0000 FFDF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
CNTx[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CNTx[15:0]: Timer x counter value
This register holds the timer x counter value. It can only be written when the timer is stopped (TxCEN
= 0 in HRTIM_TIMxCR).
Note: For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least significant bits of the counter
are not significant. They cannot be written and return 0 when read.
Note: The timer behavior is not guaranteed if the counter value is above the HRTIM_PERxR register
value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
PERx[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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