Mitsubishi Electric MELSEC iQ-R Series - Page 1411

12 MULTIPLE CPU DEDICATED INSTRUCTIONS
12.1 Another CPU Module Access Instructions
1409
12
■Applicable devices
■Control data
*1 This is the maximum setting range in a multiple CPU system consisting of two CPU modules.
It may be less than 8192 because the number of data points that can be written varies depending on the system configuration. (
Page 1401 Another CPU Module Access Instructions)
Processing details
• In a multiple CPU system, these instructions read the data in the device specified by (s2) in the host CPU module, by the
number of write data points specified by (s1)+1, and store it in the device specified by (d1) and later in another CPU module
(U/H).
• The following figure shows an outline of operation of the D(P).DDWR and M(P).DDWR instructions.
Operand Bit Word Double word Indirect
specification
Constant Others
(U)
X, Y, M, L,
SM, F, B, SB,
FX, FY
J\ T, ST, C, D, W,
SD, SW, FD,
R, ZR, RD
U\G, J\,
U3E\(H)G
Z LT, LST,
LC
LZ K, H E $
(U/H)   
(s1)   
(s2)   
(d1)   
(d2)   
Operand: (s1)
Device Item Description Setting range Set by
+0 Completion status The completion status is stored.
• 0000H: Completed successfully
• Other than 0000H: Completed with an error (error code)
 System
+1 Number of write data
points
Specify the number of write data points in units of words. 1 to 8192
*1
User
• Outline of operation of the D(P).DDWR instructions
(s1)+1
(d1)(s2)
Host CPU module
(write request source)
Another CPU module
(read target)
END0END0 END0 END0 END0END0
OFF
OFF
ON
Accept
processing
1 scan
Execution of
the instruction
Request signal
0.888ms
(default)
Data transfer Data transfer
Sequence scan
DP.DDWR instruction
Multiple CPU fixed scan
communication
Another CPU module
Completion device (d2)
Response signal