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12 MULTIPLE CPU DEDICATED INSTRUCTIONS
12.1 Another CPU Module Access Instructions
• The execution of the D(P).DDWR or M(P).DDWR instruction and whether it has been completed normally or with an error
can be checked with the completion device (d2) or completion status indication device (d2)+1.
• The number of blocks used by instructions depends on the number of write data points. For the number of blocks used by
instructions, refer to the following.
Page 1401 Another CPU Module Access Instructions
• For the specifiable target devices in the write target CPU module, refer to the following.
Page 1401 Another CPU Module Access Instructions
• If an instruction is executed while the system area has no empty block, it is completed with an error. Completion with an
error can be prevented by setting the number of blocks used by instructions in SD796 to SD799 and using SM796 to
SM799 as interlocks.
*2 This is the maximum setting range in a multiple CPU system consisting of two CPU modules.
It may be less than 8192 because the number of data points that can be written varies depending on the system configuration. (
Page 1401 Another CPU Module Access Instructions)
• Outline of operation of the M(P).DDWR instructions
• Completion device (d2)
The completion device turns on in END processing of the scan performed upon completion of the D(P).DDWR or M(P).DDWR instruction and turns off in the
next END processing.
• Completion status indication device (d2)+1
The completion device turns on or off depending on the completion status of the D(P).DDWR or M(P).DDWR instruction.
When completed normally: Unchanged from off.
When completed with an error: Turns on in END processing of the scan performed upon completion of the D(P).DDWR or M(P).DDWR instruction and turns off
in the next END processing.
When completed with an error, an error code is stored in the device (completion status) specified by (s1)+0.
Error code
(SD0)
Description
2800H The start I/O number (first three digits in four-digit hexadecimal representation) of the specified CPU module is out of the range, 3E0H to
3E3H.
2801H An invalid another CPU module is specified.
• A reserved CPU module is specified.
• An unmounted CPU module is specified.
2802H Another CPU module does not support the D(P).DDWR and M(P).DDWR instructions.
2803H The host CPU module is specified as another CPU module.
2810H A CPU module which cannot execute the instruction is specified as another CPU module.
3404H An invalid character string is used to specify a device.
3405H The number of write data points specified by (s1)+1 is out of the range from 0 to 8192.
*2
3440H The D(P).DDWR instruction is executed with the inter-CPU fixed-scan communication disabled.
3441H The specified number of data points exceeds the size of the system area that can be used by each CPU module.
Error code
((s1)+0)
Description
0010H The instruction request to the target CPU module exceeds the allowable value. (There is not empty block in the system area.)
1001H The device of another CPU module specified by (d1) cannot be used by another CPU module. Alternatively, it is out of the device range.
1080H The number of write data points that has been set by the D(P).DDWR or M(P).DDWR instruction is 0.
OFF OFF
ON
END0END0END0 END0END0
Sequence scan
MP.DDWR instruction
Another CPU module
Completion device (d2)
Execution of
the instruction
1 scan
Request signal
Accept
processing
Response signal
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